This invention relates to a data receiving system which is preferable to receive transmitted digital data for communications purpose and for data transmission between LSI circuits.
FIG. 9 shows a conventional data receiving system, according to which a received data 901 is entered into a D flip-flop (i.e., DFF) circuit 904 via a data input terminal thereof. A clock generating circuit 902 generates a clock signal 903 in synchronism with a data transmission rate of the received data 901. The clock signal 903 is entered into the DFF circuit 904 via a clock terminal thereof. The DFF circuit 904 samples the received data 901 in response to each leading edge of the clock signal 903 and generates an output signal 905 as a sampling result.
FIGS. 10A and 10B are timing charts showing the relationship among the received data 901, the clock signal 903, and the sampling result 905. In a case shown FIG. 10A, the received data 901 has a higher frequency relative to the data transmission rate of the received data 901. In the other case shown FIG. 10B, the received data 901 has a lower frequency relative to the data transmission rate of the received data 901. The received data 901 is a binary data, e.g., 0101010, whose value alternately changes between 0 and 1. T1001, T1002, T1003, T1004, T1005, T1006, T1011, T1012, T1013, T1014, and T1015 represent leading edge positions of the clock signal 903. In other words, these positions represent sampling times for the received data 901.
An operation of the above-described conventional data receiving system will be explained hereinafter. The frequency of the clock signal 903 is basically identical with that of the data transmission rate of the received data 901. However, the clock generating circuit 902 has jittered frequency characteristics. Accordingly, even if their frequencies can be regarded as identical with each other as a long-term average, their frequencies possibly cause local differences when observed in a short time duration. Such local frequency differences cause phase shifting of the sampling positions with respect to the received data 901. For example, when the frequency of the clock signal 903 is high, the sampling positions gradually shift to the left with elapsed time from the center of the received data 901 which is set at the time T1001 as shown in FIG. 10A. Only one sampling is performed for each data before the sampling time T1003. A correct sampling value is obtained from the output signal 905. However, the same data is sampled twice at successive sampling times T1004 and T1005. In this case, the output signal 905 generates the value 0 twice successively.
On the other hand, when the frequency of the clock signal 903 is low, the sampling positions gradually shift to the right with elapsed time from the center of the received data 901 which is set at the time T1011 as shown in FIG. 10B. Only one sampling is performed for each data before the sampling time T1014. A correct sampling value is obtained from the output signal 905. However, no sampling is performed for the data next to the one sampled at the sampling time T1014. Thus, the output signal 905 generates the sampling value missing the value 1 which was not sampled at the sampling time T1015.
As described above, the receiving circuit having jittered characteristics is subjected to either missing of data or double fetch of data. To solve this problem, it is necessary to use a low jitter and accurate clock.
However, according to the above-described conventional data receiving system which necessitates the use of a low jitter and accurate clock, the cost will increase.